/*
 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 
 *  
 * SPDX-License-Identifier: Apache-2.0.
 * 
 * @Date: 2021-09-15 19:45:14
 * @LastEditTime: 2021-09-27 15:09:43
 * @Description:  This files is for 
 * 
 * @Modify History: 
 *  Ver   Who        Date         Changes
 * ----- ------     --------    --------------------------------------
 */
#ifndef BSP_DRIVERS_F_SDIO_HW_H
#define BSP_DRIVERS_F_SDIO_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "ft_types.h"
#include "ft_io.h"
#include "kernel.h"

/************************** Constant Definitions *****************************/

/** @name Register Map
 *
 * Register offsets from the base address of an SD device.
 * @{
 */
#define FSDIO_REG_CNTRL_OFFSET 0x00U           /* the controller config reg */
#define FSDIO_REG_PWREN_OFFSET 0x04U           /* the power enable reg */
#define FSDIO_REG_CLKDIV_OFFSET 0x08U          /* the clock divider reg */
#define FSDIO_REG_CLKENA_OFFSET 0x10U          /* the clock enable reg */
#define FSDIO_REG_TMOUT_OFFSET 0x14U           /* the timeout reg */
#define FSDIO_REG_CTYPE_OFFSET 0x18U           /* the card type reg */
#define FSDIO_REG_BLKSIZ_OFFSET 0x1CU          /* the block size reg */
#define FSDIO_REG_BYTCNT_OFFSET 0x20U          /* the byte count reg */
#define FSDIO_REG_INT_MASK_OFFSET 0x24U        /* the interrupt mask reg */
#define FSDIO_REG_CMDARG_OFFSET 0x28U          /* the command argument reg */
#define FSDIO_REG_CMD_OFFSET 0x2CU             /* the command reg */
#define FSDIO_REG_RESP0_OFFSET 0x30U           /* the response reg0 */
#define FSDIO_REG_RESP1_OFFSET 0x34U           /* the response reg1 */
#define FSDIO_REG_RESP2_OFFSET 0x38U           /* the response reg2 */
#define FSDIO_REG_RESP3_OFFSET 0X3CU           /* the response reg3 */
#define FSDIO_REG_MASKED_INTS_OFFSET 0x40U     /* the masked interrupt status reg */
#define FSDIO_REG_RAW_INTS_OFFSET 0x44U        /* the raw interrupt status reg */
#define FSDIO_REG_STATUS_OFFSET 0x48U          /* the status reg	*/
#define FSDIO_REG_FIFOTH_OFFSET 0x4CU          /* the FIFO threshold watermark reg */
#define FSDIO_REG_CARD_DETECT_OFFSET 0x50U     /* the card detect reg */
#define FSDIO_REG_CARD_WRTPRT_OFFSET 0x54U     /* the card write protect reg */
#define FSDIO_REG_CCLK_READY_OFFSET  0x58U     /* the ciu ready */
#define FSDIO_REG_TRAN_CARD_CNT_OFFSET 0x5CU   /* the transferred CIU card byte count reg */
#define FSDIO_REG_TRAN_FIFO_CNT_OFFSET 0x60U   /* the transferred host to FIFO byte count reg  */
#define FSDIO_REG_DEBNCE_OFFSET 0x64U          /* the debounce count reg */
#define FSDIO_REG_UID_OFFSET 0x68U             /* the user ID reg */
#define FSDIO_REG_VID_OFFSET 0x6CU             /* the controller version ID reg */
#define FSDIO_REG_HWCONF_OFFSET 0x70U          /* the hardware configuration reg */
#define FSDIO_REG_UHS_REG_OFFSET 0x74U         /* the UHS-I reg */
#define FSDIO_REG_CARD_RESET_OFFSET 0x78U      /* the card reset reg */
#define FSDIO_REG_BUS_MODE_OFFSET 0x80U        /* the bus mode reg */
#define FSDIO_REG_DESC_LIST_ADDRL_OFFSET 0x88U /* the descriptor list low base address reg */
#define FSDIO_REG_DESC_LIST_ADDRH_OFFSET 0x8CU /* the descriptor list high base address reg */
#define FSDIO_REG_DMAC_STATUS_OFFSET 0x90U     /* the internal DMAC status reg */
#define FSDIO_REG_DMAC_INT_ENA_OFFSET 0x94U    /* the internal DMAC interrupt enable reg */
#define FSDIO_REG_CUR_DESC_ADDRL_OFFSET 0x98U  /* the current host descriptor low address reg */
#define FSDIO_REG_CUR_DESC_ADDRH_OFFSET 0x9CU  /* the current host descriptor high address reg */
#define FSDIO_REG_CUR_BUF_ADDRL_OFFSET 0xA0U   /* the current buffer low address reg */
#define FSDIO_REG_CUR_BUF_ADDRH_OFFSET 0xA4U   /* the current buffer high address reg */
#define FSDIO_REG_CARD_THRCTL_OFFSET 0x100U    /* the card threshold control reg */
#define FSDIO_REG_UHS_REG_EXT_OFFSET 0x108U    /* the UHS register extension */
#define FSDIO_REG_EMMC_DDR_REG_OFFSET 0x10CU   /* the EMMC DDR reg */
#define FSDIO_REG_ENABLE_SHIFT_OFFSET 0x110U   /* the enable phase shift reg */
#define FSDIO_REG_DATA_OFFSET 0x200U           /* the data FIFO access */

/** @name FSDIO_REG_CNTRL_OFFSET x0 Register 
 */
#define FSDIO_CNTRL_CONTROLLER_RESET	(0x1 << 0) /* RW To reset controller */
#define FSDIO_CNTRL_FIFO_RESET		(0x1 << 1) /* RW To reset FIFO */
#define FSDIO_CNTRL_DMA_RESET		(0x1 << 2) /* RW To reset DMA interface */
#define FSDIO_CNTRL_RES			    (0x1 << 3) /* RW */
#define FSDIO_CNTRL_INT_ENABLE		(0x1 << 4) /* RW Global interrupt enable/disable bit */
#define FSDIO_CNTRL_DMA_ENABLE		(0x1 << 5) /* RW  */
#define FSDIO_CNTRL_READ_WAIT		(0x1 << 6) /* RW Sending read-wait to SDIO cards */
#define FSDIO_CNTRL_SEND_IRQ_RESPONSE	(0x1 << 7) /* RW Bit automatically clears once response is sent. */
#define FSDIO_CNTRL_ABORT_READ_DATA	    (0x1 << 8) /* RW 读暂停异常清除 */
#define FSDIO_CNTRL_SEND_CCSD            (0x1 << 9) /* RW 发送CCD (NOT USED) */
#define FSDIO_CNTRL_SEND_AUTO_STOP_CCSD  (0x1 << 10) /* RW 发送CCD，自动STOP (NOT USED) */
#define FSDIO_CNTRL_ENDIAN		        (0x1 << 11) /* RW 0：小端，1：大端 */
#define FSDIO_CNTRL_CARD_VOLTAGE_A_MASK  GENMASK(19, 16) /* RW A电压选择 */
#define FSDIO_CNTRL_CARD_VOLTAGE_B_MASK  GENMASK(23, 20) /* RW B电压选择 */
#define FSDIO_CNTRL_ENABLE_OD_PULLUP	    (0x1 << 24) /* RW 外部开漏输出 */
#define FSDIO_CNTRL_USE_INTERNAL_DMAC	(0x1 << 25) /* RW 使用内部DMA */

/** @name FSDIO_REG_PWREN_OFFSET 0x4 Register 
 */
#define FSDIO_PWREN_ENABLE		    (0x1 << 0)  /* RW */

/** @name FSDIO_REG_CLKDIV_OFFSET 0x8 Register 
 */
#define FSDIO_CLK_SAMPLE_MASK        GENMASK(23, 16)
#define FSDIO_CLK_DRV_MASK           GENMASK(15, 8)
#define FSDIO_CLK_DIVIDER_MASK       GENMASK(7, 0)
/*
    clk_sample: 采样相位区间设置
    clk_drv: 输出相位区间设置
    clk_div: 时钟分频系数
*/
#define FSDIO_CLK_DIV(clk_sample, clk_drv, clk_div) \
    ( (FSDIO_CLK_SAMPLE_MASK & ((clk_sample) << 16)) | \
     (FSDIO_CLK_DRV_MASK & ((clk_drv) << 8)) | \
     (FSDIO_CLK_DIVIDER_MASK & (clk_div)) )

/** @name FSDIO_REG_CLKENA_OFFSET Register 
 */
#define FSDIO_CLKENA_CCLK_ENABLE		(0x1 << 0) /* RW */
#define FSDIO_CLKENA_CCLK_LOW_POWER	(0x1 << 16) /* RW */

/** @name FSDIO_REG_TMOUT_OFFSET Register
*/
#define FSDIO_MAX_DATA_TIMEOUT       0xffffff
#define FSDIO_MAX_RESP_TIMEOUT       0xff
#define FSDIO_TIMEOUT_DATA(data_timeout, resp_timeout) \
    ( (GENMASK(31, 8) & ((data_timeout) << 8)) | \
      (GENMASK(7, 0) & ((resp_timeout))) )           

/** @name FSDIO_REG_CTYPE_OFFSET Register
*/
#define FSDIO_BUS_1BITS          0x0
#define FSDIO_BUS_4BITS          0x1
#define FSDIO_BUS_8BITS          (0x1 << 16)

/** @name FSDIO_REG_INT_MASK_OFFSET Register 
 *  @name FSDIO_REG_MASKED_INTS_OFFSET Register
 *  @name FSDIO_REG_RAW_INTS_OFFSET Register
 */
#define FSDIO_INT_CD_BIT		(0x1 << 0) /* RW Card detect (CD) */
#define FSDIO_INT_RE_BIT		(0x1 << 1) /* RW Response error (RE) */
#define FSDIO_INT_CMD_BIT		(0x1 << 2) /* RW Command done (CD) */
#define FSDIO_INT_DTO_BIT		(0x1 << 3) /* RW Data transfer over (DTO) */
#define FSDIO_INT_TXDR_BIT		(0x1 << 4) /* RW Transmit FIFO data request (TXDR) */
#define FSDIO_INT_RXDR_BIT		(0x1 << 5) /* RW Receive FIFO data request (RXDR) */
#define FSDIO_INT_RCRC_BIT		(0x1 << 6) /* RW Response CRC error (RCRC) */
#define FSDIO_INT_DCRC_BIT		(0x1 << 7) /* RW Data CRC error (DCRC) */
#define FSDIO_INT_RTO_BIT		(0x1 << 8) /* RW Response timeout (RTO) */
#define FSDIO_INT_DRTO_BIT		(0x1 << 9) /* RW Data read timeout (DRTO) */
#define FSDIO_INT_HTO_BIT		(0x1 << 10) /* RW Data starvation-by-host timeout (HTO) */
#define FSDIO_INT_FRUN_BIT		(0x1 << 11) /* RW FIFO underrun/overrun error (FRUN) */
#define FSDIO_INT_HLE_BIT		(0x1 << 12) /* RW Hardware locked write error (HLE) */
#define FSDIO_INT_SBE_BCI_BIT	(0x1 << 13) /* RW Start-bit error (SBE) */
#define FSDIO_INT_ACD_BIT		(0x1 << 14) /* RW Auto command done (ACD) */
#define FSDIO_INT_EBE_BIT		(0x1 << 15) /* RW End-bit error (read)/Write no CRC (EBE) */
#define FSDIO_INT_SDIO_BIT		(0x1 << 16) /* RW SDIO interrupt for card */

#define FSDIO_INT_ALL            GENMASK(16, 0)
#define FSDIO_INT_ERR            (FSDIO_INT_RTO_BIT | FSDIO_INT_RCRC_BIT | \
                                 FSDIO_INT_RE_BIT  | FSDIO_INT_DRTO_BIT)
#define FSDIO_INT_DATA_ERR       (FSDIO_INT_DRTO_BIT | FSDIO_INT_DCRC_BIT | \
                                 FSDIO_INT_HTO_BIT | FSDIO_INT_SBE_BCI_BIT | \
                                 FSDIO_INT_EBE_BIT)
                        

#define FSDIO_DEF_INTS_CMD_MASK  (FSDIO_INT_RE_BIT | FSDIO_INT_CMD_BIT | FSDIO_INT_RCRC_BIT | \
                                 FSDIO_INT_RTO_BIT | FSDIO_INT_HTO_BIT | FSDIO_INT_HLE_BIT)
#define FSDIO_DEF_INTS_DATA_MASK (FSDIO_INT_DTO_BIT | FSDIO_INT_DRTO_BIT)

/** @name FSDIO_REG_CMD_OFFSET Register 
 */
#define FSDIO_CMD_START			BIT(31) /* 启动命令 */
#define FSDIO_CMD_USE_HOLD_REG	BIT(29) /* 0: 旁路HOLD寄存器，1: 使能HOLD寄存器 */
#define FSDIO_CMD_VOLT_SWITCH	BIT(28) /* 0: 无电压转换，1: 有电压转换 */
#define FSDIO_CMD_BOOT_MODE     BIT(27) /* 0: Mandatory boot, 1: Alternate boot */
#define FSDIO_CMD_DISABLE_BOOT  BIT(26) /* 中止boot进程 */
#define FSDIO_CMD_CCS_EXP		BIT(23) /* 0：CE-ATA 设备的中断不使能 1：使能 */
#define FSDIO_CMD_CEATA_RD		BIT(22) /* 0：主机不进行对于 CE-ATA 设备的读操作 1：进行操作 */
#define FSDIO_CMD_UPD_CLK		BIT(21) /* 1：不发送指令，仅更新时钟寄存器的值到卡时钟域内 */
#define FSDIO_CMD_INIT			BIT(15) /* 0：在发送指令前不发送初始化序列（80 个周期） 1: 发送 */
#define FSDIO_CMD_STOP_ABORT	BIT(14) /* 1：停止或中止命令，用于停止当前的数据传输 */
#define FSDIO_CMD_PRV_DAT_WAIT	BIT(13) /* 1：等待前面的数据传输完成后再发送指令 */
#define FSDIO_CMD_SEND_AUTO_STOP		BIT(12) /* 1：在数据传送结束时发送停止命令 */
#define FSDIO_CMD_STRM_MODE		BIT(11) /* 1: 流数据传输指令 */
#define FSDIO_CMD_DAT_WR		BIT(10) /* 0：读卡 1：写卡 */
#define FSDIO_CMD_DAT_EXP		BIT(9) /* 0：不等待数据传输, 1：等待数据传输 */
#define FSDIO_CMD_RESP_CRC		BIT(8) /* 1：检查响应 CRC */
#define FSDIO_CMD_RESP_LONG		BIT(7) /* 0：等待卡的短响应 1：等待卡的长响应 */
#define FSDIO_CMD_RESP_EXP		BIT(6) /* 1：等待卡的响应 */
#define FSDIO_CMD_INDX_MASK     GENMASK(5, 0)
#define FSDIO_CMD_INDX(n)		((n) & FSDIO_CMD_INDX_MASK) /* 命令索引号 */

/** @name FSDIO_REG_STATUS_OFFSET Register 
 */
#define FSDIO_STATUS_FIFO_RX		(0x1 << 0) /* RO */
#define FSDIO_STATUS_FIFO_TX		(0x1 << 1) /* RO */
#define FSDIO_STATUS_FIFO_EMPTY	(0x1 << 2) /* RO */
#define FSDIO_STATUS_FIFO_FULL	(0x1 << 3) /* RO */
#define FSDIO_STATUS_CARD_STATUS	(0x1 << 8) /* RO */
#define FSDIO_STATUS_CARD_BUSY	(0x1 << 9) /* RO */
#define FSDIO_STATUS_DATA_BUSY	(0x1 << 10) /* RO */
#define FSDIO_STATUS_DMA_ACK		(0x1 << 31) /* RO */
#define FSDIO_STATUS_DMA_REQ		(0x1 << 32) /* RO */

/** @name FSDIO_REG_FIFOTH_OFFSET Register 
 */
enum
{
    FSDIO_FIFOTH_DMA_TRANS_1  = 0b000,
    FSDIO_FIFOTH_DMA_TRANS_4  = 0b001,
    FSDIO_FIFOTH_DMA_TRANS_8  = 0b010,
    FSDIO_FIFOTH_DMA_TRANS_16 = 0b011,
    FSDIO_FIFOTH_DMA_TRANS_32 = 0b100,
    FSDIO_FIFOTH_DMA_TRANS_64 = 0b101,
    FSDIO_FIFOTH_DMA_TRANS_128 = 0b110,
    FSDIO_FIFOTH_DMA_TRANS_256 = 0b111
};

#define FSDIO_FIFOTH_DMA_TRANS_MASK  GENMASK(30, 28) /* 多次传输的突发大小 */
#define FSDIO_FIFOTH_RX_WMARK_MASK   GENMASK(27, 16) /* 当接收数据给卡时FIFO的阈值 */
#define FSDIO_FIFOTH_TX_WMARK_MASK   GENMASK(11, 0)  /* 当发送数据给卡时FIFO的阈值 */
/*
    trans_size: Burst size of multiple transaction;
    rx_wmark: FIFO threshold watermark level when receiving data to card.
    tx_wmark: FIFO threshold watermark level when transmitting data to card
*/
#define FSDIO_FIFOTH(trans_size, rx_wmark, tx_wmark)	\
    (((FSDIO_FIFOTH_DMA_TRANS_MASK) & ((trans_size) << 28)) | \
     ((FSDIO_FIFOTH_RX_WMARK_MASK) & ((rx_wmark) << 16)) | \
     ((FSDIO_FIFOTH_TX_WMARK_MASK) & (tx_wmark)))

/** @name FSDIO_REG_CARD_DETECT_OFFSET Register 
 */
#define FSDIO_CARD_DETECTED      (0x1 << 0)

/** @name FSDIO_REG_CARD_WRTPRT_OFFSET Register 
 */
#define FSDIO_CARD_WRITE_PROTECTED (0x1 << 0)

/** @name FSDIO_REG_CCLK_READY_OFFSET Register 
 */
#define FSDIO_CIU_CLK_READY     (0x1 << 0)

/** @name FSDIO_REG_UHS_REG_OFFSET Register 
 */
#define FSDIO_UHS_REG_VOLT_180	(0x1 << 0) /* RW 0: 3.3v, 1: 1.8v */
#define FSDIO_UHS_REG_DDR		(0x1 << 16) /* RW */

/** @name FSDIO_REG_CARD_RESET_OFFSET Register 
 */
#define FSDIO_CARD_RESET_ENABLE		(0x1 << 0) /* RW */

/** @name FSDIO_REG_BUS_MODE_OFFSET Register 
 */
#define FSDIO_BUS_MODE_SWR		(0x1 << 0) /* RW 软复位，复位idma内部寄存器 */
#define FSDIO_BUS_MODE_FB		(0x1 << 1) /* RW 固定burst */
#define FSDIO_BUS_MODE_DE		(0x1 << 7) /* RW idma使能 */

/** @name FSDIO_REG_DMAC_STATUS_OFFSET Register 
 */
#define FSDIO_DMAC_STATUS_TI		(0x1 << 0) /* RW 发送中断。表示链表的数据发送完成 */
#define FSDIO_DMAC_STATUS_RI		(0x1 << 1) /* RW 接收中断。表示链表的数据接收完成 */
#define FSDIO_DMAC_STATUS_FBE	    (0x1 << 2) /* RW 致命总线错误中断 */
#define FSDIO_DMAC_STATUS_DU		(0x1 << 4) /* RW 链表不可用中断 */
#define FSDIO_DMAC_STATUS_CES       (0x1 << 5) /* RW 卡错误汇总 */
#define FSDIO_DMAC_STATUS_NIS	    (0x1 << 8) /* RW 正常中断汇总 */
#define FSDIO_DMAC_STATUS_AIS	    (0x1 << 9) /* RW 异常中断汇总 */

#define FSDIO_DMAC_STATUS_ALL    GENMASK(5, 0)
#define FSDIO_DMAC_STATUS_DONE   (FSDIO_DMAC_STATUS_TI | FSDIO_DMAC_STATUS_RI | \
                                 FSDIO_DMAC_STATUS_NIS)
#define FSDIO_DMAC_STATUS_ERR    (FSDIO_DMAC_STATUS_FBE | FSDIO_DMAC_STATUS_DU | \
                                 FSDIO_DMAC_STATUS_AIS)

/** @name FSDIO_REG_DMAC_INT_ENA_OFFSET Register 
 */
#define FSDIO_DMAC_INT_ENA_TI		(0x1 << 0) /* RW 发送完成中断使能 */
#define FSDIO_DMAC_INT_ENA_RI		(0x1 << 1) /* RW 接收完成中断使能 */
#define FSDIO_DMAC_INT_ENA_FBE		(0x1 << 2) /* RW 总线错误中断使能 */
#define FSDIO_DMAC_INT_ENA_DU		(0x1 << 4) /* RW 描述符不可读中断使能 */
#define FSDIO_DMAC_INT_ENA_CES		(0x1 << 5) /* RW 卡错误中断使能 */
#define FSDIO_DMAC_INT_ENA_NIS		(0x1 << 8) /* RW 正常中断汇总使能 */
#define FSDIO_DMAC_INT_ENA_AIS		(0x1 << 9) /* RW 异常中断汇总使能 */
#define FSDIO_DMAC_INT_ENA_TX_EB     (0b001 << 10) /* RO 发送异常状态标识 */       
#define FSDIO_DMAC_INT_ENA_RX_EB     (0b010 << 10) /* RO 接收异常状态标识 */
#define FSDIO_DMAC_INT_FSM_MASK      GENMASK(16, 13) /* DMA状态机 FSM */

#define FSDIO_DMAC_INT_ALL           GENMASK(12, 0)
#define FSDIO_DMAC_DEF_INTS_MASK     (FSDIO_DMAC_INT_ENA_FBE | FSDIO_DMAC_INT_ENA_DU | \
                                     FSDIO_DMAC_INT_ENA_NIS | FSDIO_DMAC_INT_ENA_AIS )
#define FSDIO_DMAC_DONE_MASK         (FSDIO_DMAC_INT_ENA_RI | FSDIO_DMAC_INT_ENA_TI | \
                                      FSDIO_DMAC_INT_ENA_NIS)

/** @name FSDIO_REG_CARD_THRCTL_OFFSET Register 
 */
#define FSDIO_CARD_THRCTL_CARDRD		(0x1 << 0) /* RW 读卡threshold使能 */
#define FSDIO_CARD_THRCTL_BUSY_CLR	    (0x1 << 1) /* RW busy清中断 */
#define FSDIO_CARD_THRCTL_CARDWR		(0x1 << 2) /* RO 写卡threshold使能 */

/** @name FSDIO_REG_UHS_REG_EXT_OFFSET Register 
 */
#define FSDIO_UHS_EXT_MMC_VOLT	(0x1 << 0) /* RW 1.2V供电选择 */
#define FSDIO_UHS_EXT_CLK_ENA	(0x1 << 1) /* RW 外部时钟，CIU时钟使能 */
#define FSDIO_UHS_CLK_DIV_MASK   GENMASK(14, 8) /* RW 分频系数，ciu_f = clk_div_ctrl + 1, min=1*/
#define FSDIO_UHS_CLK_DIV(x)     (FSDIO_UHS_CLK_DIV_MASK & ((x) << 8))
#define FSDIO_UHS_CLK_SAMP_MASK  GENMASK(22, 16) /* RW 采样相位参数，相对于ciu时钟相位点 */
#define FSDIO_UHS_CLK_SAMP(x)    (FSDIO_UHS_CLK_SAMP_MASK & ((x) << 16))
#define FSDIO_UHS_CLK_DRV_MASK   GENMASK(30, 24) /* RW 输出相位参数，相对于ciu时钟相位点 */
#define FSDIO_UHS_CLK_DRV(x)     (FSDIO_UHS_CLK_DRV_MASK & ((x) << 24))
#define FSDIO_UHS_EXT_CLK_MUX    (0x1 << 31)

#define FSDIO_UHS_REG(drv_phase, samp_phase, clk_div) \
    ( FSDIO_UHS_CLK_DRV(drv_phase) | \
      FSDIO_UHS_CLK_SAMP(samp_phase) | \
      FSDIO_UHS_CLK_DIV(clk_div) )

/** @name FSDIO_REG_EMMC_DDR_REG_OFFSET Register 
 */
#define FSDIO_EMMC_DDR_CYCLE		    (0x1 << 0) /* RW 1: start bit小于一个周期，0：start bit 为一个周期 */

#define FSDIO_CTRL_BASE_ADDR(ctrl_p)  ((ctrl_p)->config.base_addr)
//#define FSDIO_DMA_BASE_ADDR(ctrl_p) (FSDIO_CTRL_BASE_ADDR(ctrl_p) + FSDIO_DMA_REG_OFFSET)

#define FSDIO_READ_REG(ctrl_p, reg_off)            FtIn32(FSDIO_CTRL_BASE_ADDR(ctrl_p) + (u32)(reg_off))
#define FSDIO_WRITE_REG(ctrl_p, reg_off, reg_val)  FtOut32(FSDIO_CTRL_BASE_ADDR(ctrl_p) + (u32)(reg_off), (u32)(reg_val))
#define FSDIO_SET_BITS(ctrl_p, reg_off, bit)       FtSetBit32(FSDIO_CTRL_BASE_ADDR(ctrl_p) + (u32)(reg_off), (u32)(bit))
#define FSDIO_CLR_BITS(ctrl_p, reg_off, bit)       FtClearBit32(FSDIO_CTRL_BASE_ADDR(ctrl_p) + (u32)(reg_off), (u32)(bit))
#define FSDIO_W1C_BITS(ctrl_p, reg_off, bit)       FSDIO_SET_BITS((ctrl_p), (reg_off), (bit))

#ifdef __cplusplus
}
#endif

#endif